Fabricating semiconductor integrated circuit chips (ICs) requires a large number of precisely controlled steps. Illustrative examples are forming oxide layers, printing conductor patterns (e.g. by photolithography), depositing and removing photoresist, etching circuit patterns, and implanting impurities (dopants) to form conducting regions. This is only an illustrative subset; others are known to ones of ordinary skill in the IC fabrication arts. Various fabrication tools are used to carry out these fabrication steps. Illustrative examples include stepper machines, etching machines, cleaning and dicing machines.
Various measurements and tests are performed during the IC fabrication process, generally on a random sampling basis. As known to persons of ordinary skill in the IC fabrication arts, it is physically impossible to test every feature formed by every fabrication step. After the final fabrication step, electrical performance tests are applied to the chips. Chips that pass are cut from the wafer, for subsequent packaging. Chips that do not pass are discarded. The “yield” of an IC fabrication is the percentage of the chips meeting the final electrical performance test. As known in the art, yield is crucial to the economics of IC fabrication. As one illustrative example, if an IC foundry outputs wafers with a 50% yield then, by gross averaging, approximately 50% of the foundry's resources are wasted in producing the chips.
Methods for increasing wafer yield are becoming more necessary as chip complexity increases. One reason is that increased circuit complexity generally increases the number of fabrication steps. Since defects can occur at almost any fabrication step, an increase in the number of steps operates to decrease yield. The increased number of steps also typically increases the total fabrication time. As an illustrative example, total fabrication time for a chip may exceed three months. The number of steps and fabrication time increase costs of low wafer yield. One increased cost is the “value-added” cost of the fabrication steps performed on a chip subsequent to a fatal fault in its processing.
Another increased cost is in searching for causes of chip performance deviation or low wafer yield, which may be a pattern buried within thousands of possible patterns of tools and steps. Still another example of increased cost is in migrating to, or testing a new recipe. Because of the large number of steps, and the impossibility of completely testing all wafers between fabrication steps, refining the new recipe may require substantial trial and error effort.
One method directed to reducing yield-related cost is to “bin” wafers, by measuring certain features between fabrication steps, and using the measurements to estimate the yield of the finished wafer. The estimate is based on a regression model based on measurements from previous fabrication of wafers and the wafers' respective yields. The regression model outputs an estimated yield of the tested wafer. The wafer is typically discarded if the estimated yield is below a certain minimum threshold.
There are shortcomings with these regression-type yield estimation methods. One is that such yield estimates are often not reliable. Another is that the estimates do not readily isolate which particular fabrication tool or step causes a yield problem.